The AD9361 is a high-performance, highly integrated RF Agile Transceiver™ designed for 3G and 4G base station applications. Its programmability and wide bandwidth make it an ideal choice for a wide range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrates frequency synthesizers, providing a configurable digital interface to the processor, thus simplifying design implementation. The AD9361 receiver LO operates from 70 MHz to 6.0 GHz, and the transmitter LO operates from 47 MHz to 6.0 GHz, covering most licensed and unlicensed bands. It supports channel bandwidths from less than 200 kHz to 56 MHz.

The two independent direct-conversion receivers feature best-in-class noise figure and linearity. Each receive (RX) subsystem includes independent automatic gain control (AGC), DC offset correction, quadrature correction, and digital filtering, eliminating the need to implement these functions in the digital baseband. The AD9361 also offers a flexible manual gain mode that supports external control. Each channel incorporates two high dynamic range analog-to-digital converters (ADCs) that digitize the received I and Q signals and pass them through configable decimation filters and 128-tap finite impulse response (FIR) filters, producing a 12-bit output signal at the corresponding sample rate.

The transmitter uses a direct-conversion architecture for high modulation accuracy and very low noise. This transmitter design achieves industry-leading transmit error vector magnitude (EVM) of better than -40 dB, providing significant system margin for external power amplifier (PA) selection. An on-board transmit (TX) power monitor can be used as a power detector for highly accurate TX power measurements.

Fully integrated phase-locked loops (PLLs) provide low power, fractional-N frequency synthesis for all receive and transmit channels. The channel isolation required for frequency-division duplex (FDD) systems is integrated. All voltage-controlled oscillators (VCOs) and loop filter components are also integrated. The AD9361 core can be powered directly by a 1.3 V regulator. The IC is controlled via a standard 4-wire serial port and four real-time input/output control pins. Comprehensive power-saving modes reduce power consumption to minimal levels under normal use. The AD9361 is packaged in a 10 mm × 10 mm, 144-ball chip-scale ball grid array (CSP_BGA).