1. Introduction to DMA

DMA (Direct Memory Access: Direct Memory Access) is a data transfer method that can greatly reduce the workload of the CPU. The CPU has many functions such as data transfer, calculation, and control program transfer, but in fact, transferring data (especially transferring large amounts of data) does not require CPU participation. For example, if you want the data of peripheral A to be copied to peripheral B, as long as a data path is provided for the two peripherals, and some control transfer components are added, the data copy can be completed. DMA is designed based on the above assumptions, and its function is to solve the problem of excessive consumption of CPU resources by a large number of data transfers. With DMA, the CPU can focus more on more practical operations - calculation, control, etc.

 

2. The working principle of DMA The function of DMA is to realize the direct transmission of data, and remove the link that the traditional data transmission requires the participation of CPU registers. It mainly involves data transmission in four cases, but the essence is the same, all from memory One area is transferred to another area of ​​memory (the data register of a peripheral is essentially a storage unit of memory). The four cases of data transfer are as follows:

 

 

 

peripheral to memory

 

memory to peripherals

 

memory to memory

 

Peripheral to peripheral When the user sets the parameters, which mainly involve the source address, destination address, and the amount of data to be transferred, the DMA controller will start the data transfer, and the end point of the transfer is that the remaining transfer data amount is 0 (cyclic transfer is not Such). In other words, as long as the remaining transfer data amount is not 0 and the DMA is enabled, data transfer will occur.

 

 

 

3. Does DMA affect the operation of CPU?

In an x86 architecture system, when DMA is running (say we copy a file from disk to USB), DMA will actually take a portion of the system bus cycle. That is to say, before the DMA is turned on, the system bus may be completely used by the CPU; when the DMA is turned on, the system bus should allocate a certain amount of time for the DMA to ensure that the DMA and the CPU operate at the same time. Then obviously, DMA will slow down the CPU. In the STM32 controller, the chip adopts the Cortex-M3 architecture, and the bus structure has been greatly optimized. The DMA occupies another bus and will not conflict with the CPU's system bus. That is, the use of DMA does not affect the running speed of the CPU.

 

Second, the DMA structure of STM32

1. Main features of DMA

● 12 independent configurable channels (request) 7 channels for DMA1 and 5 channels for DMA2

● Each channel is directly connected to a dedicated hardware DMA request, and each channel also supports software triggering. These functions are

software to configure.

● The priority among the seven requests can be set by software programming (there are four levels: very high, high, medium and low), if in phase

Equal priority is determined by hardware (request 0 takes precedence over request 1, and so on).

● Independent source and destination data area transfer widths (byte, half-word, full-word), simulating the process of packing and unpacking. source and destination

Addresses must be aligned by the data transfer width.

● Support circular buffer management

● Each channel has 3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error), these 3 event flags logically OR become a single interrupt request.

● Memory-to-memory transfers

● Peripherals and memory, memory and peripheral transfers

● Flash, SRAM, peripheral SRAM, APB1, APB2, and AHB peripherals can be used as the source and destination of access.

● Programmable number of data transfers: the maximum is 65536 The following is the functional block diagram: